An imager consists of an array of sensors responsive to radiant energy incident on the array. During operation of the imager, the radiant energy is incident on the sensor array for a predetermined exposure time, called the integration period, and converted to corresponding electrical charge packets which are stored in potential wells. Typically, charge packets are periodically shifted into a parallel shift register and then shifted to an output structure for external sensing.
Charge coupled device (CCD) imagers may be of the metal-oxide-silicon (MOS) type which store a charge in potential wells created either at the surface, or in a semiconductor substrate, and separated from each other by channel stops and/or by suitably applied potentials in each of two opposite directions. The charge is transported along the surface or in the substrate by the application of bias potentials to alter the configuration of potential wells.
In an X-ray imager, soft X-ray radiation energy incident on the silicon substrate is absorbed within the substrate and converted to localized electrical charge packets. The amount of charge generated is proportional to the energy absorbed. The location within the silicon substrate where this energy-to-charge conversion occurs is dependent upon the penetration depth of the energy. When the penetration depth of the radiant energy is greater than the depletion layer of the silicon substrate, for a given applied potential, charges are generated in a neutral region of the substrate outside the confines of the potential wells. Split events occur when the generated charges spread randomly due to repulsion and diffusion effects before the charges reach the potential wells. As a result, the randomly spreading charges are divided among adjacent potential wells which in turn degrades the image resolution.
One approach to reduce the diffusion effects on resolution degradation, as disclosed in U.S. Pat. No. 4,580,155, is to increase the depletion layer width in silicon for a suitable applied potential so that most of the radiant energy is absorbed within the depletion layer itself instead of in the neutral region. The electric field in the depletion layer sweeps the carriers towards the surface. This reduces the carrier transportation time and thus the amount of charge spreading due to diffusion effects. Since the depletion layer width in silicon increases with its resistivity, one way to improve the resolution is to make charge coupled imagers on high resistivity substrates.
For the near IR (wavelength from 0.8 to 1.0 microns) and soft X-ray (1 to 10 KeV) regions, substrate resistivities as high as 5 K.OMEGA.-cm are required to produce the required depletion layer width. There are a number of reported problems in fabricating charge-coupled imagers on such a high resistivity substrate. First, a resistivity drop has been reported due both to thermal degradation for processing temperatures greater than 950.degree. C. and to impurity contamination. Secondly, even if resistivity were preserved, transistors fabricated on such high resistivities cannot function due to the extremely low punch-through voltage between source and drain. However, due to performance requirements, charge detection is only practical with on-chip transistor circuitry. The invention of U.S. Pat. No. 4,580,155 provides adjacent regions of high resistivity and low resistivity on the same chip, wherein a charge coupled array is fabricated in the high resistivity region and an output circuit is fabricated in the low resistivity region.
Another effort in the CCD imager art, such as for example, U.S. Pat. No. 4,963,952, has been directed toward the elimination of dark current by using a multipinned phase charge coupled device. In the invention of U.S. Pat. No. 4,963,952, the siliconsilicon dioxide interfaces of a back-illuminated CCD are passivated by biasing the Si--SiO.sub.2 interfaces in the front and back. On the front multiphase-gate side, biasing and pinning the phase-clocked array gates into inversion (hence the term "multipinned-phase") causes holes to populate at the interface, thus eliminating surface dark current generation. However, to avoid adverse effects in full well capacity, implanting p dopants in the areas confined beneath one or more of the phase-clocked gates is necessary, thus providing a potential difference between the phased gates to allow charge to gather in collecting sites free of extra dopant while maintaining the inverted condition, and thereafter transferring the charges from well to well during readout. On the backside of the CCD, the Si--SO.sub.2 interface is passivated by negative biasing a metal flash gate to heavily populate the interface with holes. This eliminates backside dark current and directs photogenerated carriers away from the back to the front where they are collected in wells and then transferred out under control of multiphased clocks. An additional advantage of negative biasing on the metal flash gate is that the bias may be used as a shutter to control the rate of exposure.
Still another effort in the CCD imager art, as disclosed in U.S. Pat. No. 4,286,591, is a CCD imager of the field transfer type having a surface channel A register for storage and transfer of charges, having a B register of either a buried channel or surface channel type for temporary storage of field charges shifted from the A register, and having a buried channel CCD C register coupled to the B register for receiving charge signals, in parallel, a row at a time, from the B register.
Still other efforts in the CCD art have been directed toward, for example: reducing CCD chip power dissipation, as in U.S. Pat. No. 4,903,284; improving charge transfer, as in U.S. Pat. No. 4,819,067; and using a CCD as a memory device, as in U.S. Pat. No. 4,225,947.